Update History
V1.5.0
/ 8-January-2016
Main
Changes
- MISRA C 2004 rule 5.1 and rule 10.6 compliancy.
- Several renaming in order to be aligned with the Reference Manual.The list of the modification is listed hereafter :
- Adding of a new COMP_Common_TypeDef structure.
- Removal of the RCR field inside the TIM_TypeDef structure.
- Adding of a new define COMP12_COMMON
- Adding of a new define DAC1 (same as DAC)
- Adding of a new define ADC1_COMMON
- Adding of a new define ADC_CHSELR_CHSEL
- Adding of a new define COMP_CSR_WINMODE
- Adding of a new define DAC_CHANNEL2_SUPPORT
- Renaming of EXTI_RTSR_TRx into EXTI_RTSR_RTx with x = {0,..22}
- Renaming of EXTI_FTSR_TRx into EXTI_FTSR_FTx with x = {0,..22}
- Renaming of EXTI_SWIER_SWIERx into EXTI_SWIER_SWIx with x = {0,..22}
- Renaming of EXTI_PR_PRx into EXTI_PR_PIFx with x = {0,..22}
- Renaming of RCC_IOPRSTR_GPIOxRST into RCC_IOPRSTR_IOPxRST with x = {A,B,C,D,E,H}
- Add a new define RCC_AHBRSTR_DMA1RST
- Add a new define RCC_APB2RSTR_ADC1RST
- Add a new define RCC_APB2RSTR_DBGMCURST
- Renaming of RCC_IOPENR_GPIOxEN into RCC_IOPENR_IOPxEN with x = {A,B,C,D,E,H}
- Add a new define RCC_AHBENR_DMA1EN
- Rename RCC_APB2ENR_MIFIEN into RCC_APB2ENR_FWEN
- Rename RCC_APB2ENR_ADC1EN into RCC_APB2ENR_ADCEN
- Rename RCC_APB2ENR_DBGMCUEN into RCC_APB2ENR_DBGEN
- Rename RCC_IOPSMENR_GPIOxSMEN into RCC_IOPSMENR_IOPxSMEN with x = {A,B,C,D,E,H}
- Add a new define RCC_AHBSMENR_DMA1SMEN
- Rename RCC_APB2SMENR_ADC1SMEN into RCC_APB2SMENR_ADCSMEN
- Rename RCC_APB2SMENR_DBGMCUSMEN into RCC_APB2SMENR_DBGSMEN
- Add new defines TIM_TIM2_REMAP_HSI_SUPPORT and TIM_TIM2_REMAP_HSI48_SUPPORT
- Remove
the following defines : TIM_CR2_CCPC, TIM_CR2_CCUS,
TIM_CR2_OIS1, TIM_CR2_OIS1N, TIM_CR2_OIS2,TIM_CR2_OIS2N,
TIM_CR2_OIS3, TIM_CR2_OIS3N, TIM_CR2_OIS4
- Remove TIM_SR_COMIF and TIM_SR_BIF
- Remove TIM_EGR_COMG and TIM_EGR_BG
- Remove TIM_CCER_CC1NE, TIM_CCER_CC2NE and TIM_CCER_CC3NE
- Remove TIM_RCR_REP
- Rename USART_ISR_LBD into USART_ISR_LBDF
- Rename WWDG_CR_Tx into WWDG_CR_T_x with x = {0,..6}
- Rename WWDG_CFR_WDGTBx into WWDG_CFR_WDGTB_x with x = {0,1}
- Add
several macros to check Timer instances (For exemple
IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(),IS_TIM_CLOCK_DIVISION_INSTANCE(),
etc..)
V1.4.0
/ 16-October-2015
Main
Changes
- Update
all the files to support STM32L011xx and STM32L021xx.
- Remove the Debug Monitor handler from the startup files (not supported on L0).
- Renamings and usage of some aliases in order to be compliant with the RefManuals.
V1.3.0
/ 9-Sept-2015
Main
Changes
- Update
all the files to support STM32L031xx and STM32L041xx.
- Several renamings in order to be compliant with the specifications.
- Adding of new bit definitions (COMP_CSR_COMP2LPTIM1IN1, SYSCFG_CFGR1_UFB, I2C_OAR2_x, LCD_CR_MUX_SEG, RTC_BKP_NUMBER)
- Update of several registers and structures (CRC_TypeDef, TIM_TypeDef)
V1.2.0
/ 6-February-2015
Main
Changes
- Added
the set of CMSIS files for the STM32L07xx and STM32L08xx family and the
set of startup files for IAR/Keil/Atollic IDEs
- Add
IAR set of files STM32L073xx
- STM32L072xx - STM32L071xx - STM32L083xx - STM32L082xx - STM32L081xx
- Added
MDK-ARM startup files for L071xx, L072xx, L073xx, L081xx, L082xx, L083xx
- Added
Atollic startup files for L071xx, L072xx, L073xx, L081xx, L082xx, L083xx
V1.1.0
/ 18-June-2014
Main
Changes
-
Header
files
- Add
defines for memories
base and end addresses: FLASH_END, DATA_EEPROM_BASE
and DATA_EEPROM_END
(instead of having them in stm32l0xx_hal_flash.h
file)
- Peripheral
register structures definition is aligned on 32 bit
-
system_stm32l0xx.c
V1.0.1
/ 24-April-2014
Main
Changes
- Update gcc
startup files.
V1.0.0
/ 22-April-2014
Main
Changes
License
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AND ANY EXPRESS OR IMPLIED WARRANTIES,
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PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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For
complete documentation on STM32 Microcontrollers
visit www.st.com/STM32
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